The present invention is related to the field of processing systems, and more particularly to buses used in processing systems to interconnect a processor with other devices.
In processing systems, it is necessary for a processor to communicate with other system elements such as memory, control/status registers, peripheral devices, etc. It is common to employ a "bus", or shared multi-wire connections, as a communications transport mechanism for such purposes.
There are certain features of known buses that are advantageous in certain kinds of processing systems. For example, buses intended for widespread use by different vendors have relatively complex signaling and data transfer mechanisms, in order to support a variety of types of devices and/or processors. Also, buses commonly provide for data transfer in different directions at different times, necessitating the use of bidirectional bus interface logic at some or all connection points to the bus. Bidirectional buses are especially useful for communication among different physical devices such as different integrated circuits, which have a limited number of package pins.
However, the above characteristics of known buses can be disadvantageous in other environments. In a complex integrated circuit (IC) having an on-chip bus, for example, the use of complex bus protocols and bidirectional data transfer make it difficult to verify the correctness of the IC design, and can also impair testability during manufacture. Accordingly, there is a need for a bus that is particularly suitable for on-chip use, and which avoids reliance on bidirectional data transfer.